1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including differential amplifying means for amplifying input signals.
This application is counterpart of Japanese patent application, Serial Number 36659/2004, filed Feb. 13, 2004, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A configuration of a differential amplifier circuit having a conventional constitution will be explained with reference to FIG. 13. The circuit 1300 shown in the same figure includes a differential amplifier circuit group 1310 and a final-stage differential amplifier circuit 1320, a detection (DET) circuit 1330 that detects an output 1320 of the differential amplifier circuit, and a bias circuit 1340. The output of the bias circuit 1340 is connected to a comparator 1350.
The differential amplifier circuit group 1310 is a circuit group in which a circuit similar to the differential amplifier circuit 1320 is included thereinside and connected in plural form. Therefore, an internal configuration of the differential amplifier circuit 1320 will be described. In the differential amplifier circuit 1320, a constant current circuit (PTn) connected to a power supply VDD is connected to respective source terminals of a PMOS transistor P(n1) and a PMOS transistor P(n2). Drain terminals of these transistors are connected to a ground GND via a resistor PR(n1) and a resistor PR(n2) respectively. Incidentally, “n” indicates the whole number indicative of the number of connecting stages of the differential amplifier circuits 1320.
An input PIN(1) or an output P0(n1) from a pre-stage circuit is connected to the PMOS transistor P(n1) and an input PIN(2) or an output P0(n2) from a pre-stage circuit is connected to the PMOS transistor P(n2).
Connecting points of the drain terminals of the PMOS transistors P(n1) and P(n2) and the resistors PR(n1) and PR(n2) respectively form the outputs P0(n1) and P0(n2) of each differential amplifier circuit and are connected to the input of the nest-stage differential amplifier circuit. An output P0(n2) of the differential amplifier circuit placed in the final stage is connected to the detection circuit 1330.
In the detection (DET) circuit 1330, a source follower circuit is formed by both a constant current circuit (PT) 1332 connected to the power supply VDD, and a PMOS transistor 1334 having a source terminal to which the constant current circuit (PT) 1332 is connected, a gate terminal to which the output signal P0(n2) of the differential amplifier circuit PAn is connected and a drain terminal connected to the ground GND. An output 1336 for outputting a detect signal DET is outputted from the source terminal of the PMOS transistor 1334. Also the output 1336 is connected to the ground GND via a condenser 1338. The output (DET) 1336 of the detection circuit 1330 is connected to the comparator 1350.
The bias circuit 1340 includes a constant current circuit 1342 connected to the power supply VDD and a resistor 1344 connected between the output of the constant current circuit 1342 and the ground GND. The bias circuit 1340 outputs a bias signal BP from a connecting point 1346 at which the potential is determined by a current value of the constant current circuit 1342 and the resistance value of the resistor 1344. The bias signal BP is sent to the comparator 1350 where it serves as a reference potential of the comparator 1350. In the comparator 1350, the bias signal BP of the bias circuit 1340 is inputted to the input thereof on the plus (+) side, and the output signal DET of the DET circuit 1330 is inputted to the input thereof on the minus (−) side. The comparator 1350 compares these inputs and outputs an output signal (COMPOUT) to an output 1360.
A circuit, which comprises these differential amplifier circuit group (PA) 1310, differential amplifier circuit (PAn) 1320, detection (DET) circuit 1330, bias circuit 1340 and comparator 1350, has the relationship of a positive phase and a negative phase with respect to the input PIN(1) and the input PIN(2). When an amplitude-modulated signal is inputted thereto, output signals (P0n1) and (P0n2) amplified by the differential amplifier circuit group (PA) 1310 and the differential amplifier circuit (PAn) 1320 are outputted. The output signal (P0n2) delivered from the detection (DET) circuit 1330 is peak-detected on the amplitude Low side by the source follower circuit of the detection (DET) circuit 1330 and the condenser 1338 thereof, followed by demodulation. The demodulated signal is sent to the comparator 1350 as a detect signal (DET). The bias circuit 1340 generates a bias-signal (BP) corresponding to an intermediate potential between an “H” signal of the detect signal (DET) and an “L” signal thereof and supplies it to the comparator 1350. In the comparator 1350, a signal antiphase to the detect signal (DET) is brought to a signal between the power supply VDD and the ground GND.
A conventional configuration of a differential amplifier circuit shown in FIGS. 14 and 15 made use of a configuration wherein a plurality of differential amplifier circuits PA1 through PAn (where n: the number of connecting stages of differential amplifier circuits) were connected and a final-stage differential amplifier circuit was connected to an automatic gain control (AGC) circuit. Incidentally, both figures are combined together as shown in FIG. 16.
Described specifically, the differential amplifier circuits PA1, PA2, . . . , PAn respectively include PMOS transistors (Pn) each having a source terminal to which a power supply VDD is connected and a gate terminal to which a bias signal input (PB) 1410 is connected, and PMOS transistors (Pn1), (Pn2), (Pn3) and (Pn4) each having a source terminal to which a drain terminal of the PMOS transistor (Pn) is connected.
The drain terminals of the PMOS transistors (Pn1) and (Pn3) are interconnected with each other and connected to the ground GND via a resistor (PRn1). Also the drain terminals of the PMOS transistors (Pn1) and (Pn4) are interconnected with each other and connected to the ground GND via a resistor (PRn2). The gate terminals of the PMOS transistors (Pn3) and (Pn4) are interconnected with each other and connected with a connecting line 1420 for inputting an AGC signal.
The differential amplifier circuits PA1 through PAn configured of these PMOS transistors (P1(P2 through Pn)), (P11(P21 through Pn1)), (P12(P22 through Pn2)), (P13(P23 through Pn3)), (P14(P24 through Pn4)) and resistors (PR11(PR21 through PRn1)) and (PR12(PR22 through PRn2)) output outputs P011(P021 through P0n1) from nodes to which the drain terminals of the PMOS transistors (P11(P21 through Pn1)) and (P13(P23 through Pn3)) are connected, and output outputs P012(P022 through P0n2) from nodes to which the drain terminals of the PMOS transistors (P12(P22 through Pn2)) and (P14(P24 through Pn4)) are connected, respectively.
An input PIN(1) for inputting an input signal PIN(1) is connected to the gate of the PMOS transistor (P11) of the first-stage differential amplifier circuit PA1. An input PIN(2) for inputting an input signal PIN(2) is connected to the gate terminal of the PMOS transistor (P12).
Outputs P011 through P0(n-1)1 of the pre-stage differential amplifier circuits are connected to their corresponding gate terminals of the PMOS transistors (P21) through (Pn1) of the second-stage and later differential amplifier circuits PA2 through PAn. Outputs P012 through P0(n-1)2 of the pre-stage differential amplifier circuits are connected to their corresponding gate terminals of the PMOS transistors (P22) through (Pn2). An output signal P0n2 outputted from the output of the final-stage differential amplifier circuit PAn is inputted to the AGC circuit 1430.
The automatic gain control (AGC) circuit 1430 includes a PMOS transistor 1432 having a source terminal to which the power supply VDD is connected and a gate terminal to which a bias signal input (PB) is connected, and a PMOS transistor 1434 connected to a drain terminal of the PMOS transistor 1432. The output P0n2 of the differential amplifier circuit PAn is connected to its corresponding gate terminal of the PMS transistor 1434, and its drain terminal is connected to the ground.
A node at which the drain terminal of the PMOS transistor 1432 and the source terminal of the PMOS transistor 1434 are connected, constitutes an output 1440 that outputs a gain control signal (AGC). The output 1440 is also connected to the ground GND via a condenser 1450. The gain control signal (AGC) outputted to the output 1440 is supplied to the respective differential amplifier circuits PA1 through PAn.
In the circuit comprising these differential amplifier circuits PA1 through PAn and the AGC circuit 1430, a sine wave is inputted to the input PIN(1) and a sine wave antiphase to that at the input PIN(1) is inputted to the input PIN(2). A signal amplified by each of the differential amplifier circuits PA1 through PAn is transmitted to the AGC circuit 1430 as an output signal P0n2 of the final-stage differential amplifier circuit PAn. The output signal P0n2 is inputted to the gate terminal of the PMOS transistor 1434 of the AGC circuit 1430 and raised by a VT potential of the PMOS transistor. The Low-side peak of the amplified sine wave is detected by the condenser 1450 so that a gain control signal (AGC) is outputted. The gain control signal (ABC) is inputted to the gate terminals of the PMOS transistors (P13(P23 through Pn3)) and (P14(P24 through Pn4)) of the differential amplifier circuits PA1(PA2 through PAn), respectively.
When the potential of the gain control signal (AGC) is sufficiently higher than the potentials of the signals inputted to the gate terminals of the PMOS transistors (P11(P21 through Pn1)) and (P12(P22 through Pn2)) in the differential amplifier circuits PA1(PA2 through PAn), the currents equivalent to ½ of current values defined by the PMOS transistors (P1(P2 through Pn)) respectively flow into the PMOS transistors (P11(P21 through Pn1)) and (P12(P22 through Pn2)). The gains and potentials of the output signals P011(P021 through P0n1) and P012(P022 through P0n2) are respectively determined based on the current values of the PMOS transistors (P11(P21 through Pn1)) and (P12(P22 through Pn2)) and the resistance values of the resistors (PR11(PR21 through PRn1)) and (PR12(PR22 through PRn2).
When the gain control signal (AGC) becomes low, the current flows into each of the PMOS transistors (P13(P23 through Pn3)) and (P14(P24 through Pn4)). Therefore, the currents that flow through the PMOS transistors (P11(P21 through Pn1)) and (P12(P22 through Pn2)) become small and hence the gains of the output signals P011(P021 through P0n1) and P012(P022 through P0n2) become low. At this time, their output potentials remain unchanged.
Thus, when the amplitudes of the input signal PIN(1) and the input signal PIN(2) has changed, the potential of the gain control signal (AGC) varied correspondingly, thereby changing the gains of the differential amplifier circuits PA1 through PAn, whereby a stable output signal could be obtained.
Patent Document 1    Japanese Unexamined Patent Publication No. Hei 3(1991)-278110
In such a conventional circuit configuration shown in FIG. 13, however, when, for example, the total gain of the differential amplifier circuits of n stages is 80 [dB] and a very small ASK-modulated wave which is 30 [μV] at the maximum amplitude and 3 [μV] at the minimum amplitude with respect to each of the input PIN(1) and the input PIN(2), is inputted, a signal amplified to a maximum amplitude of 300 [mV] and a minimum amplitude of 30 [mV] is outputted to the output P0n2 of the differential amplifier circuit (PAn). In this case, the output signal P0n2 sent to the detection (DET) circuit 1330 is peak-detected by the source follower circuit and the condenser 1338 and raised by the VT potential of the PMOS transistor 1334, after which it is demodulated into a signal having an amplitude of 135 [mV], which in turn is outputted as a detect signal (DET).
In the bias circuit 1340, the current value of the constant current circuit 1342 and the resistor 1344 are set in such a manner that an intermediate potential of the amplitude 135 [mV] of the detect signal DET is reached, whereby a bias (BP) signal is outputted. When, at this time, a VT variation range of the PMOS transistor is ±100 [mV], for example, the VT potential of the PMOS transistor 1334 varies. Therefore, the DET signal of the detection (DET) circuit 1330 is affected by the VT variations and hence the output potential of the DET signal varies within the range of ±100 [mV].
On the other hand, since the output signal of the bias circuit 1340 is not affected by the VT variations of the PMOS transistor, the output signal results in a constant value even where the VT variations of the PMOS transistor take place.
A problem arises in that the detect signal (DET) varies within the range of ±100 [mV] when the VT variations take place in these ways, whereas since the amplitude of the detect signal (DET) is 135 [mV], the bias (BP) signal does not fall into the middle of the amplitude of the detect signal (DET) so that the output signal (CMPOUT) of the comparator 1350 can not provide or reach an expected value.
In the circuit configuration of the prior art shown in FIGS. 14 and 15, the output voltage of each of the differential amplifier circuits PA1 (PA2 through PAn) remains unchanged where the VT value of the PMOS transistor varies, whereas the potential of the gain control signal (AGC) changes by the VT variations as a result of the PMOS transistor 1434 provided within the AGC circuit 1430 being affected by the VT variations. Therefore, a problem arises in that when the VT variations of the PMOS transistor take place, the gain of each of the differential amplifier circuits PA1 (PA2 through PAn) inputted with the gain control signal AGC changes, so that a stable output signal is not obtained.